1. Field of the Invention
The present invention relates to a method for correcting a mask pattern to be formed on a photomask used in a photolithographic step of a semiconductor device fabrication process, a photomask, a method for fabricating a photomask, an electron beam writing method for fabricating a photomask, an exposure method, a semiconductor device, and a method for fabricating a semiconductor device.
2. Description of the Related Art
A photomask used in a photolithographic step of a semiconductor device fabrication process includes a glass substrate transparent to exposure light and a patterned light-shielding or semi-translucent light-shielding thin layer on top of it.
In a semiconductor device fabrication process, a mask pattern formed on the photomask is transferred to, for example, a photoresist formed on a semiconductor substrate. Hereinafter, a pattern formed on a photomask is also referred to as a “mask pattern”, data including a plurality of design patterns is also referred to as “design pattern data”, pattern data for electron beam writing is also referred to as “writing pattern data”, and a pattern formed on a resist is also referred to as a “resist pattern”.
For example, design pattern data for fabricating a photomask is composed in a stream format known as GDSII/Stream in which a design pattern is expressed by a polygon or in a writing format known as OASIS in which a design pattern is expressed by only a rectangle and a trapezoid.
When, for example, a mask pattern is transferred to a photoresist formed on a semiconductor substrate by irradiating a photomask with exposure light, the optical proximity effect appears. Therefore, the shape of a pattern formed on the photoresist is different from that of the design pattern.
That is, in a photolithographic step of a semiconductor device fabrication process, when a mask pattern having a size substantially the same as the wavelength of exposure light is transferred to a photoresist, an interference effect of the exposure light becomes noticeable. Thus, the optical proximity effect appears that causes the dimension of a pattern formed on the photoresist to be different from that of a design pattern, which is a problem.
The optical proximity effect appears in the form of a line width reduction or the shrinkage of a terminal end portion of an isolated pattern (e.g., isolated line), which reduces the controllability of a gate line width and alignment margin. As a result, the variation in transistor characteristics of semiconductor devices increases and the production yield of chips decreases. That is, the productivity of semiconductor device fabrication significantly decreases.
As the wavelength of exposure light becomes shorter, this problem becomes significant. To accommodate a fine design rule, an automatic optical proximity effect correction (OPC) system using an optical intensity simulation base has been developed.
By correcting the optical proximity effect, a desired linewidth can be obtained when, for example, a mask pattern is transferred to a photoresist formed on a semiconductor substrate by irradiating a photomask with exposure light and the exposure light is properly focused. However, when the exposure light is not in focus, a required contrast cannot be obtained. Accordingly, the desired linewidth cannot be obtained. Since the linewidth is reduced, an open error including disconnection and poor contact may occur.
Japanese Unexamined Patent Application Publication No. 2001-100390 and Japanese Unexamined Patent Application Publication No. 2002-131882, for example, disclose methods for preventing the occurrence of such a problem.
A photomask pattern correction method discussed in Japanese Unexamined Patent Application Publication No. 2001-100390 includes a first step, a second step, and a third step. In the first step, a first pattern which is used in a photolithographic step of a semiconductor device fabrication process and which requires a precise dimension control is dimension-corrected so that the dimensions of the first pattern become the desired dimensions after transferred to a wafer. In the second step, a second pattern of the mask pattern which does not require a precise dimension control is dimension-corrected so that the dimensions of the second pattern become the desired dimensions after transferred to the wafer. In the third step, an auxiliary pattern is selectively provided for only the first pattern.
In addition, Japanese Unexamined Patent Application Publication No. 2002-131882 discloses a mask pattern correction method in which the linewidth of a pattern is increased so that the pattern is not optically isolated.
However, even when the mask pattern correction method disclosed in Japanese Unexamined Patent Application Publication No. 2001-100390 is applied, a case in which an auxiliary pattern cannot be arranged occurs due to a critical dimension design rule defining a minimum interval and a minimum line length required for generation and arrangement of the auxiliary pattern. Furthermore, even when the mask pattern correction method disclosed in Japanese Unexamined Patent Application Publication No. 2002-131882 is applied, the minimum linewidth and minimum interval of lines, in some cases, are not ensured. Consequently, it is difficult to increase the linewidth of a pattern in order not to be optically isolated.